Alpexpo Grenoble, France  /  October 25, 2016  -  October 27, 2016

Fraunhofer IZM at the SEMICON 2016

http://semiconeuropa.org/

Booth 662

Together with other Fraunhofer Institutes from the Microelectronics Alliance Fraunhofer IZM will again be presenting its latest developments from the realm of wafer level packaging technologies.

The focus is on:

  • Wafer Level MEMS Packaging
  • Wafer-to-wafer bonding
  • Flexible multi-layer HD substrates
  • Silicon interposers
  • Through silicon vias
  • High-density  redistribution
  • Wafer thinning

Fraunhofer IZM’s ASSID group (All Silicon System Integration Dresden) will be presenting its activities in 3D wafer level packaging and wafer stacking.

 

Come and see us, our booth number is 662.

Flexible multi-layer HD substrate
© Fraunhofer IZM
Flexible multi-layer HD substrate
3D integrated clocking MEMS module using TSV technology in CMOS
© Fraunhofer IZM/ Volker Mai
3D integrated clocking MEMS module using TSV technology in CMOS
Enhanced wafer thinning and stress relief technologies for ultra-thin wafers (> 20 µm)
© Fraunhofer IZM
Enhanced wafer thinning and stress relief technologies for ultra-thin wafers (> 20 µm)