EMC Modeling and Design of Packages, Particularly Signal and Power Distribution Networks
Integration density keeps increasing to meet the ever rising demand for miniaturized electronic products. A number of strategies are used to make this possible, including mounting the components as compactly as possible, using interconnects with smaller widths and less pitch and applying advanced 3D integration techniques such as chip stacks. However, high-density integration when combined with operating frequencies over 1 GHz can cause electromagnetic reliability (EMR/EMC) problems such as reduced signal and power integrity, electromagnetic interference (EMI) and electromigration.
Our research group develops methods for analyzing, quantifying and minimizing EMR/EMC problems at chip, package and PCB levels. Examples of EMR/EMC problems include reflection, delay, attenuation, crosstalk, current crowding, simultaneous switching noise (SSN) and consequent cross-coupling.
This is especially true of signal and power distribution networks (SDNs and PDNs). Traditionally, design and optimization of the chip, package and board are tackled separately. However, in the microwave range, the interaction between the SDNs and PDNs can impede system performance.
Our research develops techniques for modeling and optimizing SDNs and PDNs on chip, package and board level as entire systems at the very beginning of the design cycle. We analyze the interaction between the components of the two networks very carefully and develop measures for minimizing any EMR/EMC problems or interference.