Wafer Level System Integration

Fraunhofer Institute for Reliability and Microintegration

High Density Interconnect & Wafer Level Packaging & All Silicon System Integration Dresden ASSID

Wafer level packaging and system integration has been one of Fraunhofer IZM´s key competences for many years.According to the technical requirements of future microelectronic products specific 3D system integration becomes one of the main drivers and the most promising technologies for heterogeneous system integration.

The department "Wafer Level System Integration" with it's facilities in Berlin and Moritzburg/Dresden focuses on the development and application of Wafer level System Integration technologies which includes Wafer level Packaging (WLP), Chip Size Packaging (CSP), thin film technology and as well 3D integration using Through Silicon Vias (TSVs). The department is embedded in Fraunhofer IZM's overall strategy of heterogeneous system integration and is a well established partner in the worldwide network for advanced wafer level system integration technologies.

The department operates two clean room facilities in Berlin and Dresden with latest state of the art equipment from 100 to 300mm wafer sizes. The department cooperates with equipment manufacturers, material supplier and end users of microelectronic products, from all over the world to realize world class wafer level packaging solutions. The well-established technology branches offer development, prototyping and small-volume production as a service within the realms of MCM-D, wafer-level CSP with redistribution layer (RDL), 3D integration and wafer-level bumping for flip chip assembly to industrial partners and customers.

All Silicon System Integration Dresden (ASSID)
Fraunhofer IZM-ASSID - All Silicon System Integration Dresden- is part of the department "Wafer Level System Integration" and has been established with a focus on advanced wafer level packaging and system integration technologies, especially with respect to 3D wafer level system integration using Through Silicon Vias (Cu-TSC). ASSID operated a leading edge 300 mm wafer process line for TSV formation, 3D device stacking and assembly. The facility is equipped with leading edge process tools according to industrial requirements for manufacturing. The service includes customer specific development and prototyping, low volume manufacturing and process transfer as well.

Specific focus of ASSID are Cu-TSV process integration (Via middle, last process), Silicon interposer for heterogeneous device integration, wafer level assembly and 3D stack formation.

With major equipment and material suppliers also specific Joint Development Projects are settled up to meet the targets for next generation 3D wafer level integration.

Fraunhofer IZM-ASSID
Telefon +49 351 795572-0
Fax +49 351 795572-19
Ringstr. 12, 01468 Moritzburg

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