Within the framework of the High Performance Center »Functional Integration in Micro- and Nanoelectronics«, Fraunhofer IZM-ASSID developed a novel approach to combine the advantages of rigid and flexible components in one Si substrate.
In this approach, flexible, polymer-based wiring layers and interconnects are processed on 300mm silicon wafers. After thinning the wafers, silicon is removed from the wafer backside, exposing designated areas of the polymer layers. These areas are now flexible and can be folded after electronic components are assembled.
This technology allows the creation of a TSV-free compact Wafer Level Packages for applications which require medium packaging densities.