GlObal, Flexible, On demand and Resourceful Timing IC & MEMS Encapsulated System

Overall goal of the project was the development of manufacturing concepts for highly stable, generic, low-cost timing devices suitable for power aware, long autonomy and portable telecommunication systems such as mobile phones. One milestone in this project was the wafer-level fabrication of a MEMS package consisting of an active CMOs wafer with vertical copper-filled TSVs and bonded cap wafers for hermetic sealing of resonator components.




Together with its industrial and academic partners, Fraunhofer IZM develops base technologies for the wafer level fabrication of low-cost, miniature, chip-scale packaged (SCP) hybrid microsystems.For this purpose, standard technologies like redistribution, TSV formation and wafer to wafer bonding are combined to obtain versatile approaches for hermetic wafer level packaging of MEMS components. Within the project Fraunhofer IZM evaluated the described approach for wafer level packaging of generic timing micro systems. The systems include a special designed timing ASIC build in TSMC 180 nm technology, a miniature quartz tuning fork with 131 kHz resonance frequency as well as a 2 GHz bulk acoustic wave (BAW) filter device.

The ASIC wafers were processed with 100 µm deep Cu TSVs in a front side via last regime. During back side processing of the ASIC wafers proper gold structures for assembly of the quartz components and gold/tin frame structures for bonding of the cap wafers were ceated.

The fabricated cap wafers had a thickness of 400 µm. On these wafers, gold metal frames which match in pitch and lateral dimensions to the frames at the AISC were created. Inside these frames 200 µm deep recesses were etched to generate space for the quartz crystals. Both, ASIC and cap wafers were bonded together in vacuum with standard wafer bonding equipment using a gold/tin soldering regime. After the wafer bonding step, the BAW filter devices were mounted on the ASIC wafer front side using reflow soldering.

Depending on wafer format, with such a wafer level packaging approach up to several 10k MEMS devices can be herme­tically packaged in parallel at one wafer.


  • Micro Crystal AG
  • Politecnico di Milano
  • ST Italy
  • TU Delft
  • VTT



Top view of the created SiPs with a size of 1,64 x 1,25 x 0,65 mm³
Cross-sectional view of wafer level packaged timing micro system based on TSV CMOS IC bonded with silicon cap, hermetically sealed quartz crystal and top side mounted BAW filter

General Project Information

Go4Time is a project funded by the European Commission under the Seventh Framework Programme (FP7)  call 5.9: "Microsystems and Smart Miniaturised Systems"