Fraunhofer IZM-ASSID Presents Innovative Solutions for 3D System Integration at SEMICON Japan 2026

Tokyo Big Sight, Japan | German Pavilion / December 09, 2026 - December 11, 2026

Fraunhofer IZM-ASSID Presents Innovative Solutions for 3D System Integration at SEMICON Japan 2026

www.semiconjapan.org

Fraunhofer IZM, along with its division “All Silicon System Integration Dresden” (ASSID), will be represented at SEMICON Japan in Tokyo from December 9–11, 2026. In the German Pavilion, the research center will showcase innovative technologies and the latest developments in the fields of 3D wafer-level system integration, advanced packaging, and heterogeneous integration.

The Fraunhofer IZM-ASSID in Dresden is one of the world’s leading research centers for 3D wafer-level system integration. Using an industry-oriented 300-mm process line, the institute develops customized solutions for the integration of complex microelectronic systems. Research activities include, among other things, through-silicon via (TSV) technologies, high-density rewiring, wafer-level assembly, and 3D chip stacking. The goal is to enable high-performance, compact, and reliable electronic systems for future applications.

SEMICON Japan is one of the most important international trade shows in the semiconductor industry and brings together companies, research institutions, and experts from across the entire semiconductor value chain. The trade show will celebrate its 50th edition in 2026 and offers a platform for exchanging ideas on current technologies, trends, and future developments in semiconductor manufacturing.

Exhibits at a Glance

3D Wafer-Level System Integration: Silicon Interposer with TSVs and Microfluidic Channels for Chip Cooling

This exhibit demonstrates the integration of microfluidic cooling channels into a silicon interposer. The technology enables heat dissipation of up to 700 watts and combines liquid cooling with through-silicon vias (TSVs) for power delivery. Integrated test structures also support technological characterization and reliability assessment.

Fan-0ut WLP Project USeP: Processor and Sensors

This exhibit showcases a compact fan-out wafer-level packaging solution for integrating a RISC-V processor with various sensors. On a package area of just 10 × 10 mm, sensor functions for pressure, acceleration, temperature, and gases, among others, are combined with high-performance electrical interconnect technologies. This example illustrates the possibilities of heterogeneous integration of multifunctional electronic systems.

Fan-In WLP Project USeP: Processor and Memory

This exhibit illustrates the integration of a processor test chip with two memory chips using fan-in wafer-level packaging technology. With a package size of 10 × 10 mm and a height of just 0.77 mm, the design enables a compact arrangement of multiple semiconductor components. The development showcases approaches for space-saving and highly integrated electronic systems.

Si Test Interposer | Project USeP

The silicon test interposer is used to investigate and evaluate high-density electrical interconnect technologies in fan-out wafer-level packaging. With approximately 2,200 micropillar contacts and a fine contact array, it provides a platform for characterizing flip-chip interconnects, re-wiring layers, and other assembly and interconnect technologies.

Visit us in Tokyo!

Discover the latest developments from Fraunhofer IZM-ASSID and learn how innovative packaging and integration technologies are enabling the next generation of microelectronic systems.

We look forward to seeing you at the German Pavilion at SEMICON Japan 2026 and to discussing these topics with you in person!

SEMICON Japan

Tokyo Big Sight, Japan | German Pavilion / December 09, 2026 - December 11, 2026