Preparation Techniques 3D Stack
A new method allows the simultaneous preparation of any number of TSVs.
The evaluation of 3D interconnects in silicon is commonly done by time-consuming and extensive FIB cuts that usually visualize a single TSV only. Fraunhofer IZM has developed a new preparation technique that allows the simultaneous precise cutting and polishing of large areas of any number of TSVs. With this approach, the etch profile in silicon, isolation layer, barrier & seed layer and the microstructure along the whole via can be captured representatively with high contrast and a very detailed resolution.