Cu-TSV Interposer

Exhibit by IZM-ASSID

Multi-Project-Wafer to enable electrical characterization of high frequency applications. 16 sub projects on reticle: - Wide I/O DRAM design study - Inductivity arrays - TSV capacitor arrays - TSV daisy chains - Interconnect design studies

Silicon Interposer with Cu-TSV and high density redistribution layer and integrated passive devices enabling electrical characterization of high frequency applications.

  • Full filled Cu-TSV  (diameter  10 µm / depth 120 μm ASR:12)
  • Multi-layer-redistribution Cu/Polymer (3 layers)
  • Integrated passive devices
  • Flip chip compatible micro interconnects (bumps)

Multiproject approach 

  • Wide I/O DRAM design study
  • Inductivity arrays
  • TSV capacitor arrays
  • TSV daisy chains
  • Interconnect design studies
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List of Services for 300/200 mm wafers
  • Full Cu-TSV and Cu liner TSV integration in active CMOS device
  • TSV process integration: via-last back side and front side / via-middle / via first
  • Dry etch incl. wet cleaning: DRIE, RIE of Si and Dielectrics
  • Isolation liner deposition: SATEOS, PETEOS, PESilan, PESiN
  • Barrier/seed-layer deposition PVD: Ti, Ta, Cu, TiN, WTi and  MOCVD: TiN, Co
  • TSV metallization: Cu-ECD
  • Metal anneal up to 400°C
  • Front side / back side contact  formation
  • Basic design guidelines (diameter / depth):
    • min. 5 μm / 50 μm
    • typ. 10 μm / 120 μm
    • 20 μm / 120μm
    • Back side TSV (Cu-liner) up to 250 – 700 μm depth