Fan-Out Wafer Level Packaging

Singulated known good dies can be reconfigurated in a molded wafer. Fraunhofer IZM has developed an RDL processing technology on molding wafers with emebedded silicon chips. This allows an individual wafer level packaging for single chip devices which are cutted out from multi-project wafer after FEOL processing.  Small chips with high I/O count can be embedded in a molding to generate a larger die molding chip with a Fan-Out routing to realize a cost effective matching to the large pitch of PCBs. Multi-chip embedding and wafer level routing enable the ultra high-density wafer level systems-in-package with low inductance. The low loss characteristic of the molding makes the Fan-Out wafer level packaging attractive for high efficient RF-applications.

The embedding of chips in a mold compound and the implementation of wafer-level technologies in such kind of substrates is a very topical issue. This technology not only enables simplified of solder bumps routing of single chips, but also allows the integration of heterogeneous chip types in a package in the narrowest of spaces. For this, demonstrators have been realized for a customer. Here, the electrical interconnects between the chips are realized directly in thin film redistribution layers. By avoiding wirebonds or bumps the parasitic effects could be noticeably minimized compared to conventional setups. These characteristics make this approach attractive for embedding especially for high frequency systems. The low softening point of currently used mold compound requires a continuous low-temperature processing for the realization of the redistribution layers whic hcan be realized with a photosensitive dry film dielectric.

Fan-Out WLP demonstrator for RF application

Cross-section Fan-Out WLP demonstrator for RF application