Fan-Out Wafer Level Packaging

Fan-out refers to embedding chips in a mold compound to produce reconfigured wafer substrates and applying wafer-level technologies. This technology not only offers solutions for equalizing the solder contacts of individual chips, but also provides an approach for integrating heterogeneous chip types in a package with maximum contact density in a very small space.

 

Your partner for fan-out wafer-level packaging

Fraunhofer IZM is one of the leading research institutions in the field of fan-out wafer-level packaging and has a comprehensive process landscape covering all modern forms of this technology. The focus is on the development of high-performance, miniaturized, and heterogeneously integrated electronic systems, which are realized through reconfigured wafer structures and high-precision redistribution layers (RDL).

IZM is one of the few institutes that has demonstrated both Chip 1st /Mold 1st approaches and sophisticated RDL-1st processes on an industrial scale. This combination opens up a high degree of technological flexibility and allows the implementation of a wide variety of packaging architectures for sensor technology, power electronics, RF modules, HPC, or IoT systems.

 

Technological flexibility for maximum applications

The work carried out by IZM covers a wide range of demanding applications. These include RF modules for 5G and mmWave technologies, the integration of power semiconductors such as GaN and GaAs ICs, and fan-out-based system-in-package solutions, including the integration of cooling concepts. MEMS and sensor systems have been successfully embedded in fan-out structures, using special process variants to protect sensitive surfaces and ensure reliable packages. 3D packaging solutions are implemented in fan-out solutions using through mold vias (TMVs) or Through package vias (TPVs).

 

Everything from a single source

At Fraunhofer IZM, companies benefit from a complete process chain from a single source – from design support, molding, RDL manufacturing, and assembly to comprehensive reliability characterization. The institute offers customer-specific developments as well as prototyping and small-batch production, provides support in material and process selection, and implements projects in an industry-relevant environment. All in all, Fraunhofer IZM offers a powerful and broad range of services that sets the standard for modern electronics development and heterogeneous integration. 

© Fraunhofer IZM
Process Flow for Fan-Out Packaging Chip-1st and RDL-1st/ Chip-last
© Fraunhofer IZM
FOWLP Example – Hyteck Projekt
© Fraunhofer IZM
FOWLP GaN & GaAs Integration – SMART3 Projekt
© Fraunhofer IZM | Volker Mai
FOWLP for photonic packaging with integrated one PIC and eight ICs – PUNCH Projekt
© Fraunhofer IZM
RDL-1st with through package vias
© Fraunhofer IZM | Volker Mail
universal sensor platform (USeP) for Industrial IoT

Relevant Projects & Initatives

Packaging of ultra-dynamic photonic switches and transceivers

Project Punch (2022-2026)

Initiative for chiplet technology in the automotive sector

CHASSIS (2025-2028)

Wafer Level Packaging Angebot within APECS

Publication List

  • Braun, T., Becker, K.-F., Hoelck, O., Voges, S., Kahle, R., Dreissigacker, M., & Schneider‑Ramelow, M. (2019). Fan‑Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration. Micromachines, 10(5), Article 342.
  • Wöhrmann, M., Dreissigacker, M., Braun, T., Schiffer, M., & Schneider‑Ramelow, M. (2023). A novel FOWLP method to integrate delicate MEMS components. Proceedings of the 73rd ECTC.
  • Gernhardt, R., Wöhrmann, M., Ganesh, U., Adler, M., Lambert, B., Schneider‑Ramelow, M., Braun, T., & Riedl, J. (2025). Seamless Heterointegration of Components: Advancements in Fanout Technology and Thermal Solutions in System in Package. IEEE Electronics Packaging Technology Conference (EPTC).
  • Braun, T., Becker, K.-F., Hoelck, O., Voges, S., Kahle, R., Dreissigacker, M., & Aschenbrenner, R. (2019). Fan‑Out Wafer Level Packaging – A Platform for Advanced Sensor Packaging. IEEE ECTC.
  • Braun, T., Becker, K.-F., Hoelck, O., Voges, S., Kahle, R., & Schneider‑Ramelow, M. (2014). Fan‑Out Wafer Level Packaging for MEMS and Sensor Applications. ITG/GMA Symposium.
  • Woehrmann, M., Braun, T., Toepper, M., & Lang, K.-D. (2018). Ultra‑Thin 50 µm Fan‑Out Wafer Level Package: Development of an Innovative Assembly and De‑bonding Concept. IEEE ECTC.
  • Braun, T., Hoelck, O., Voitel, M., Obst, M., Voges, S., Becker, K.-F., Aschenbrenner, R., & Schneider‑Ramelow, M. (2023). A Closer Look to Fan‑Out Panel Level Packaging. IEEE EDTM.
  • Dreissigacker, M., Wöhrmann, M., Lieske, D., & Braun, T. (2025). Fan‑Out WLP in Europe – Towards a European Manufacturing Supply Chain. EMPC.
  • Braun, T., Hölck, O., Obst, M., Voges, S., Adler, M., Becker, K.-F., Wöhrmann, M., Gernhardt, R., Tschoban, C., Ndip, I., Voitel, M., Müller, F., Dreissigacker, M., & Schneider‑Ramelow, M. (2023). Fan‑Out Wafer Level Packaging Solutions for mmWave Applications. EPTC Invited Talk.
  • Braun, T., Böttcher, M., Schiffer, M., Pötter, H., Brockmann, C., Becker, K.-F., Freimund, D., & Schneider‑Ramelow, M. (2023). Universal IoT Sensor Platform (USeP) – RDL‑First Approach