Worldwide Network

Panel Level Packaging Consortium

Focus Project: Process Optimization and Cost Modelling

Key benefits

Actual exploitation remains one of the top-line concerns and limits of FOPLP technology. The project intends to expand the current cost model with a granular routing model, also covering  other packaging architectures and opportunities for introducing the required software adjustments with an eye on ease of use.

Main goals

  • Reviewing the entire process flow with consideration for variations and interactions in the processes and materials
  • Producing handling and automation concepts
  • Designing and preparing test vehicles
  • Capturing market and technology trends and establishing a networking platform
  • Expanding the current cost model


The consortium includes a dedicated corporate membership category for commercial partners. Individual payment plans are available on request, with cancellation options from year 2. The membership fee covers the fundamental research in all R&D activities.

Research Results

  • Participation in the research project’s steering and controlling
  • One-on-one technology transfer


  • Quarterly workstream reports
  • Half-yearly management and technical reports


  • Quarterly virtual meetings online
  • Half-yearly on-site meetings in Berlin, including in-depth workshops on specific topics

A Look Back at the Previous Consortium
(2016 - 2019)

Fraunhofer IZM’s expertise in wafer level packaging and substrate technology represented the nucleus from which the Panel Level Packaging Consortium grew to include 17 industrial partners in its original incarnation in 2016. The international consortium achieved its headline goals and made significant technical progress in the field of large-area fan-out panel level packaging.

All partners contributed to the progress and success of the PLP consortium. Several test layouts were designed for process development on panel sizes of 18”x 24”. The implementation and improvement of die shift compensation and the monitoring and evaluation of thickness and warping were made possible in a joint effort of the different workstreams, using over 300,000 test chips. A combination of wafer-level (thin film) processing and PCB-like substrate processing was developed for this metal routing process.

An automated electrical test routine was successfully implemented for the demonstrators. Building on the technological progress, a complex cost  model was introduced to allow cost analysis and calculation at a granular level of detail in the reference applications, including process, material and design options, panel utilization, and scalability.