Worldwide Network

Panel Level Packaging Consortium

Focus Project Frame Thrust Process Optimization Including Cost Model

Key benefits

Exploitation is one of the overall technology interactions and limits of FOPLP. In addition, the focus is on the extension of the cost model by a fine line routing model and to other packaging architectures. This will also include a user friendly software modification.

Main goals

  • Process considerations along the entire process flow including process and material variations and interactions
  • Handling and automatization concepts
  • Design and test vehicle preparation
  • Study of market and technology developments and networkingplatform
  • Extension of the cost model

Membership

Within the Consortium there will be one company membership category. Individual payment plans are available on request. There will be a cancellation clause for the 2nd year. This membership fee covers the fundamental research in all R&D.

Research Results

  • Participation in research project steering and controlling
  • One-on-one technology transfer

Reports

  • Quarterly thrust report
  • Half yearly management and technical reports

Meetings

  • Quarterly web-meeting
  • F2F meeting in Berlin twice a year, including in-depth workshops on specific topics

Review of the previous Consortium (2016 - 2019)

Fraunhofer IZM’s expertise in wafer level packaging and substrate technology was the nucleus to start the Panel Level Packaging Consortium with 17 industrial partners in 2016. This international Consortium has achieved the overall goals of the project and significant technical progress in the field of large area fan-out panel level packaging.

All partners have contributed to the progress and success of the PLP consortium. Several test layouts were designed forprocess development on panel sizes of 18”x 24”. The implementation and improvement of the die shift compensation as well as the warpage and thickness measurement and evaluation were a joint effort of the different thrusts using over 300,000 test chips. For this metal routing process a fusion of wafer-level (thin film) processing and PCB like substrate processing was developed.

An automated electrical test routine was successfully implemented for the demonstrators. In addition to the technical progress a complex cost  modelling has been successfully implemented allowing the cost calculation and analysis with fine granularity of reference applications taking into account process, material and design options, panel utilization and scalability.