Actual exploitation remains one of the main concerns and limits of FOPLP technology. The project intends to expand the current cost model with a granular routing model, also covering other packaging architectures and opportunities for introducing the required software adjustments with an eye on ease of use.
Focus Project Thrust 1
Exploiting die placement and embedding technology for fine line wiring FOPLP.
Focus Project Thrust 2
Exploiting the technology limits of the fine line wiring.
Focus Project Thrust 3
Exploiting the migration limits of the fine line wiring.
The physical background of these migration phenomena is not new, but larger dimensions are less prone to defects. Therefore miniaturization of the wiring to 2 μm lines/space may face physical/chemical limitations.
Material migration is driven by concentration gradient, temperature gradient, electrical field and mechanical stress Cu is far more resilient to electro-migration compared to Al, but Cu has a much higher tendency to migrate through the dielectric layer further increased by humidity.
The consortium includes a dedicated corporate membership category for commercial partners. Individual payment plans are available on request, with cancellation options from year 2. The membership fee covers the fundamental research in all R&D activities.
Fraunhofer IZM’s expertise in wafer level packaging and substrate technology represented the nucleus from which the Panel Level Packaging Consortium grew to include 17 industrial partners in its original incarnation in 2016. The international consortium achieved its headline goals and made significant technical progress in the field of large-area fan-out panel level packaging.
All partners contributed to the progress and success of the PLP consortium. Several test layouts were designed for process development on panel sizes of 18”x 24”. The implementation and improvement of die shift compensation and the monitoring and evaluation of thickness and warping were made possible in a joint effort of the different workstreams, using over 300,000 test chips. A combination of wafer-level (thin film) processing and PCB-like substrate processing was developed for this metal routing process.
An automated electrical test routine was successfully implemented for the demonstrators. Building on the technological progress, a complex cost model was introduced to allow cost analysis and calculation at a granular level of detail in the reference applications, including process, material and design options, panel utilization, and scalability.