Online Course at IWLPC 2020 / October 29, 2020, 8:30am PST
From Wafer to Panel Level Packaging #
Panel Level Packaging (PLP) is one of the latest trends in microelectronics packing. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package also approach larger substrates formats. These are targeted in this course. Manufacturing is currently done on wafer level up to 12”/300 mm and 330 mm respectively. For higher productivity and therewith lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, PLP might be the next big step. PLP has the opportunity to adapt processes, materials and equipment from other technology areas. Printed Circuit Board (PCB), Liquid Crystal Display (LCD) or solar equipment is manufactured on panel sizes and offer new approaches also for PLP. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. This course will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well as Panel Level Packaging including Fan-out Panel Level Packaging substrate embedding approaches. This will include materials discussion, technologies, applications and market trends as well as cost modelling.
- Introduction to Advanced Packaging
- Trends in Wafer Level Packaging
- Fan-In and Fan-out Wafer Level: Material; Processes and Application
- Introduction and Definition of Panel Level Packaging
- Fan-out Panel Level Packaging: Technologies, Challenges and Opportunities
- Substrate Embedding Technologies
Who should attend:
Anyone who is interested in Advanced Packaging, Fan-in and Fan-out Wafer Level Packaging and the transition to Panel Level Packaging. Engineers and managers are welcome as detailed technology descriptions as well as market trends, applications and cost modelling are presented.