Current research into assembly technologies focuses on the mounting of SMDs down to 008004, area array packages, and flip-chips, with the smallest chips reaching edge lengths of 180µm, monolithic processors up to 40x40 mm², or chiplets. Additionally, the handling of voltage sensitive MEMS components is being researched. A range of substrates is used for mounting, from conventional PCBs to flex or 3D stack solutions with exceptional precision for mounting sensor components. For Fan-Out Wafer / Panel-Level Packaging, bare dies can be mounted quickly and precisely on large-format carriers (up to 610x457 mm² PCB formats).
Available technologies include the application of solder balls for bumping chips, wafers, and area array packages.
Active research into method development for Industry 4.0 or AI/ML-driven process optimization benefits from the “Material dosing – mounting – reflow” process chain.