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Exhibit by IZM-ASSID
Double sided processed 12" wafer with structures enabling electrical characterization of high frequency applications
Test structures on a 12" wafer
High Density Multi-Layer 12" Flex Substrates
Enhanced wafer thinning and stress relief technologies for ultra-thin wafers (> 20 µm).
Die to Wafer (D2W) technology on 12" wafers
3D chip stacking (1+9) with TSV test dies
for Material Characterization
SiP with ASIC and MEMS on Si TSV interposer (100 μm)
double-sided liquid cooling technology by innovatively integrating horizontal and vertical microfluidic channels
Exhibits by IZM-ASSID
with Si Interposer, realized within the public funded project Admont
Exhibits by IZM
Multiproject-wafer with 66 Fan-in WLP realized within the project USeP