Embedding & Substrate Technologies

The EST group works to develop innovative means for embedding power semiconductors(Si, SiC, GaN) in substates used in automotive, server, and industry applications. Embedding allows the precise placement of components before lamination in an epoxy / fibre matrix. Electronic connections are created with galvanically filled Cu vias, followed by photolithography for structuring the copper layers.

The technology can create extremely short connections that minimize inductance and switching losses. One of its great advantages is the ability to directly integrate heat management structures, with the resulting hermetic encapsulation giving the components optimum protection and enabling highly compact power modules with exceptional thermal and mechanical reliability.

Embedding technology allows the creation of highly integrated heterogeneous systems for RF, analogue, and digital applications like 5G or radar. The work of the EST group uses vacuum lamination to embed semiconductor chips (e.g. GaAs, SiGe) or complex circuits with different SMD components directly in multilayer boards. The choice of material (cores and pre-pregs) depends on the application’s specific needs in terms of dielectric parameters, thermal stability, or mechanical qualities.

Key advantages include the massive increase in functional density and improved signal integrity as a result of shorter interconnects, while also making the systems more robust. Conventional mounting is an option on the exterior, enabling complex System-in-Package (SiP) or stacked (PoP) architectures. This approaches significantly improves performance and paves the way e.g. for the high-frequency communication applications of the future.

High-resolution copper structures blow < 5 µm L/S on organic substrates enable high-density connections for silicon chips and mainboards. The technology responds to today’s increasingly demanding requirements in terms of I/O density and signal integrity. The EST working group develops build-up processes for a range of dielectric films (incl. ABF). Semi-additive processing (SAP) is used to form tiny conductive structures in the 2 to 5 µm range. Conventional subtractive approaches can achieve resolutions of between 10 and 20 µm with mask-less direction integration, and vertical vias with diameters below 25 µm are created by laser ablation and plasma etching. The working group also creates technological modules for embedded copper structures (damascening technique).

These approaches serve to massively increase integration density when compared to traditional substrative processes, while keeping signal losses and space requirements low, e.g. for wearables and high-performance systems.

Glass substrates are being investigated as a means to exceed the physical limits of organic materials for large-format high-end packages (>100 mm), e.g. for AI accelerators. Glass offers superior dimensional stability (minimal warpage) and extremely smooth surfaces for ultra-fine RDL structures. The EST group creates glass substrates with Through-Glass Vias (TGV) using laser-induced deep etching (LIDE). Metallization is achieved by sputtering or chemical deposition with subsequent copper electroplating or bottom-up processes. Rewiring layers are created with ABF films or unfilled dielectrics.

With its extreme stability, glass allows record I/O density and improved signal integrity even at considerable thermal loads.

Precise processing allows significant performance advantages over conventional organic IC substrates.

Embedding is one of the core competences of the EST working group, covering both SMD and bare-die embedding.

SMD embedding is used to mount different SMD components, including passive, QFNs, or FPGAs on one or more of the interior layers of a board, to be subsequently laminated into the stack. The advantages of this approach include a substantial reduction in the height of such systems, which are made more robust at the same time.

In bare-die embedding, chips are first mounted on a layer specific to the given application (e.g. power or RF), laminated, and then connected by micro-vias. The resulting design is robust, but also benefits from the shorter connectors and consequently increased performance.

Applications

• SMDs, prepackaged components like QFNs
• Bare dies: HF, III/V Chip, Power

Production Formats:

• Full format: 18“x24“: 610 x 457 mm²
• Quarter format: 9“x12“: 303 x 227 mm²

Specifications:

• Track resolution: >= 20 µm L/S
• Blind via: >= 50 µm
• Layers: <= 10

The EU-funded SPIDER project will use the world’s first majority logic gate using magnetic spin wave interference for a real-world application. The concept has, to date, only be demonstrated in practice as a separate element with supporting lab peripherals. For n-bit addition, a high-performance organic interposer is used as an interface with a proprietary CMOS chip and a spin wave chip, using YIG material on a GGG substrate. For this to work, more than 30 RF connectors need to be synchronized in phase. The resulting hybrid system shows how novel computing platforms can be combined with conventional electronics to reap all of the benefits of the different parts of the system.

Official website: https://spider-horizon.eu/

The Glass Panel Technology Group, headed by Fraunhofer IZM, works on technologies for novel glass-core substrates as replacements for organic materials. Planar and stable glass has critical advantages for precise, high-density connections and chip or chiplet integration. Compared to silicon interposers, glass can be used for large-format panels to make production more efficient. The project covers the entire process chain from forming through-glass vias (TGVs) to mounting the system. It is set up to model scalable, industry-scale production and validate the reliability of the concept in live demonstrators. Currently, sixteen industry partners are included in the network, sharing knowhow across the value chain and working towards a shared technology roadmap.

Official website: Tech News – Glass Panel Technology Group launched under the leadership of Fraunhofer IZM

X-TREME 6G is a leading European industry consortium, set up to establish a groundbreaking open microelectronics platform in Europe. Its goal is to design and develop disruptive next-generation chiplet and chipset designs for 6G applications, using the entire potential of first-rate silicon BiCMOS, InP, and heterogener 3D integration for high-capacity radio access. This includes wireless backhaul in the sub-THz range, joint communication and sensing, non-terrestrial networks and Networks-as-a Sensor (NaaS). The Fraunhofer EST group is working on the heterogeneous packaging platform for InP-PA/LNA/transceivers and SiGe-BiCMOS transceivers with Antennas-in-Package (AiP), using PCB embedding technologies for D-band and H-band as mmWave Front-End-Module (FEMs), which will also be used for heat dissipation for the RF FEMs. The EST group intends to develop the FEM heterogeneous platform for 18"×24“ panels to prepare them for IZM’s APECS pilot line and later transfer to industry.

Official website: https://x-treme6g.eu/

The EU-funded SPIN CHIP project was set up to combine several spintronics components like memory, magnetic field sensors, neuronal networks, and direct RF processing on a single platform. The project is taking each specific technology to the next level in terms of sophistication and performance, with IZM focusing on the highly sensitive and compact magnetic field sensors. The IZM’s role on the project also includes the development of a standard integration platform for all technological components, including the interface with a conventional CMOS logic. The project’s mission is to make it simpler to configure system by combining different components for economically viable production in Europe.

Official website will follow (project launch: 01 June 2026)

Alongside the specific sensor technology, PROACTIF is developing custom integration technologies. The long-range radar is made with a combination of mold technologies for high-performance 3D antennas and LTCC ceramic packaging for front-end integration. The purpose of the LTCC is to dissipate the power losses of the amplifier stage, while adding its own positive electrical and thermo-mechanical qualities.

The short-range radar and multi-sensor integration in general require innovative, optimized circuit board technology. The unique shape of the drone’s interior calls for a flexible board design, including the use of rigid-flex boards. The flexible layers are made from RF-ready materials like RF-PI (polyimide) or LCP (Liquid Crystal Polymer) as well as other flexible substrates made with thermoplastic polyurethane (TPU).

Official website: https://proactif-project.eu

The entire facilities are designed as a flexible research and development line, equipped with cutting-edge hardware.

For each client, the architecture of the assemblies, the choice of materials, and even the hardware parameters can be adjusted in custom ways and/or from our catalogue of standard processes.

Research and construction projects are:

• defined in our digital process management system (PMS)
• produced in formats suited for touchless formats in ESD-shielded and locked containers
• digitally recorded and documented

We can employ the integrated in-house processing facilities:

• Plating (incl. surface refining, etching / wet chemistry),
• Substrate integration (incl. pressing, drilling, laser processing),
• Cleanroom (incl. lithography, plasma processing)

Our standard formats:

• Quarter format: 12“ x 9“ 303 x 227 mm²
• Half format: 18“ x 12“ 457 x 303 mm²
• Full format: 24“ x 18“ 610 x 457 mm²
• SEMI standard: 20“ x 20“ 510 x 515 mm²

Other formats on request

Ramgraber Plating Line 1

• (Chemical) de-smearing
• Direct copper metallization
• DK and BV filling
• Bond films

Ramgraber Line 2

• Surface finishes incl. ENIG, ENEPIG, and DIG

Schmid etching and stripping line

• Etching copper structures
• Stripping photo resists

Lemmen

• Etching titanium and copper structures
• Chemical silver plating
• Brown oxide

Konntec

• Flux residue removal

Analytics

• Titration
• X-ray fluorescence analysis
• Atomic emission spectroscopy
• Cyclical voltametric stripping analysis (CVS)
• UV/Vis spectroscopy
• Light microscopy

Lamination
Applying build-up, resist, and solder resist films

• Vacuum lamination press Dynachem
• Triple roll laminator Dynachem

Digital lithography
Strukturierung von Fotolacken & -Filmen

• Schmoll Ultra MDI (L/S: 2µm)
• Orbotech KLA Ultra 200 (L/S: 8/12µm)

Plating
Copper plating, resist removal

• LAM Research Kallisto

Sputtering
Seedlayer deposition Ti, Cu, TiW etc.

• CREAVAC CREAMET CSL3 600 PVD

Dry edging
Processing vias and trenches, dry de-smearing, dry de-scumming

• EVATEC PNL 600 RIE Modul

Analytics
Fault analysis, quality control

• AOI Onto Firefly
• AOI CONFOVIS Panel Inspect
• Flying probe tester ATG A9+
• Light microscopy

Video – Cleanroom at Fraunhofer IZM 

Laser processing
Drilling microvias, cutting

• Pico Blade Schmoll (UV)
• Trotec Spedy (CO2)

Mechanical processing
Milling, drilling, metal, organics, FR4 material

• 2 x Schmoll MX1
• Schmoll MX1 - Metal

Lamination
Component embedding with pre-pregs and construction of multiplex PCBs

• Lamination press Lauffer 125/4
• High-temperature press Lauffer

Plasma processing
Surface activation (O2) and cleaning (Ar, CF4, N, O2)

• Nordson March PCB 800

3D printing

• Keyenece Agilista

Analytics
Fault analysis, quality controls

• AOI | CMM IMPEX pro X3
• Flying probe tester SPEA 4040
• Flying probe tester ATG A9
• Light microscopy
• GE Nano X-ray analysis

VIDEO – LAB TOUR Substrat integration LINE