Wafer Level Integration
The use of wafer level assembly and packaging technologies is already well-established in many different products. All processing is carried out on wafer level, however, only once the actual semiconductor processing has been completed. The first step in this design approach is manufacturing chip-sized packages (CSPs) with widths barely larger than those of the chips. A redistribution layer is added to manufacture I/O pads with larger pitch, and subsequently additional active and passive components are integrated. Here, passive components such as resistors, capacitors and inductors are included on the IC using thin-film processes. With the aid of bumping processes, standard mounting (gluing, soldering) is performed, so that the components can be integrated in later standard SMD processes.
We are currently conducting intensive development of (sub) systems on ICs and wafer level molding concepts. In the future, functional layers will play a larger role. For example, extremely thin components will be integrated in cavities, polymer layers and capacitors using honey comb structures.